资源列表
CodeLock
- 用于模仿密码锁的工作过程。完成密码锁的核心控制功能。可实现数码输入、清除、退位、设置密码、错误提示、系统报警、解除报警、系统关闭等功能。-Used to imitate the work of the code lock process. Locks achieve the core control functions. Digital input can be achieved, clear, step down, set a password, error message, the syst
task1
- A simple multiplexor
module-mf
- verilog Implementation of Mean filter to implement in FPGA
Nios2
- 这是一个基于NIOS II的LED控制的使用了PS/2键控的源代码-This is a NIOS II of the LED control based on the use of the PS/2 source code keying
lunaRotation
- 这里是对图像旋转的讲解和相关的matlab程序。还有相应的PPT供大家学习。-Here is the explanation of the image rotation and related matlab program. PPT also appropriate for them to learn.
PWM_modem
- 8bit PWM encoder and decoder, the zip includes PWM timing and both decoding and encoding modules. The system will run perfectly on any CPLD or FPGA. Documentation regarding the design is also included.
Cabad
- MPEG-4/AVC - H.264 CABAC decoder written in VHDL and synthesis on a Virtex 5
matrix
- Implement the Matrix function about 16bits on FPGA BOARD
programmablpulsegenerator
- 用VHDL编译的源代码，可编程脉冲生成器，解压后直接用Quartus打开project即可-Compiled with VHDL source code, programmable pulse generator, after extracting the direct use of Quartus can open the project
vhdl_iir
- vhdl 代码实现的 iir 滤波器 包括 并行 流水线结构 超前进位结构-iir filter vhdl code to achieve parallel pipelined structure of ultra-ahead structure
miaobiao
- 用动态扫描方法和定时器1在数码管的前三位显示出秒表， 精确到1 秒，即最后一位显示1 秒，一直循环下去 设时钟频率为12M-With dynamic scanning method and Timer 1 in the top three shows digital stopwatch, accurate to 1 of the second and final one shows 1 seconds, the clock has been set down cycle freque
verilogRS
- 该文件为基于fpga的RS（204.188）译码器的verilong源代码，使用的Quartus II的开发环境，已经通过编译，需要者可以自己下载在编译简历工程使用-The document is based on fpga' s RS (204.188) decoder verilong source code, use the Quartus II development environment, has been compiled by the need to download th