资源列表
binary_adder_tree_vhd
- This an reconfogurable binary Adder and this is the base for another modules in vhdl
johnson
- johnson计数器是一种同步计数器，每一次之变化一位，具有最简的组合逻辑电路。-johnson counter is a synchronous counter, each followed by a change, with the most simple combinational logic circuit.
crc32
- 循环冗余校验码，CRC32算法的Verilog代码-Cyclic redundancy check code, CRC32 algorithm Verilog code
hz
- 万能频率器，可以修改其中的参数，可是实现任意的分频！很方便！-Universal frequency, you can modify one of the parameters, but any implementation of the sub-band! Very convenient!
Seven-Segment-Decoder
- 用VHDL语言在FPGA上实现将十进制bcd码转换成七段led显示码-FPGA using VHDL language to achieve will be converted to decimal bcd yards led seven segment display code
universal_counter
- This a universal counter with up/down signal,min_tick,max tick. it s written with generics so every one can use it.-This is a universal counter with up/down signal,min_tick,max tick. it s written with generics so every one can use it.
honglvdeng
- Verilog HDL作为一种规范的硬件描述语言,被广泛应用于电路的设计中。他的设计描述可被不同的工具所支持,可用不同器件来实现。利用Verilog HDL语言自顶向下的设计方法设计交通灯控制系统，使其实现道路交通的正常运转，突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点，并通过Xilinx ISE6.02和ModelSim5.6完成综合、仿真。此程序通过下载到FPGA芯片后,可应用于实际的交通灯控制系统中。-Verilog HDL as a standard hardware
pso-vhdl2
- i want verilogHDL and VHDL source coding.please help me-i want verilogHDL and VHDL source coding.please help me..
CLA_4
- 用verilog语言编写的CLA_4文件。CLA_4是4位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 4 files. CLA 4 is a four-ahead adder source code after the code verification function correctly, readers can write their own testbench code for ver
ALU.vhd
- Desarrollo de la Unidad Légica Aritmética (ALU) en VHDL
spi
- SPI接收模块，被注释掉的是发送模块，需要进一步地完善-SPI receiver module
top_lcd_key
- fpga控制lcd12864液晶显示，以及矩阵键盘的控制-the use of lcd12864 and keyboard