资源列表
IIR
- 环路滤波器的FPGA实现，使用VERILOG语言，ISE13.2编译环境-The loop filter FPGA realizing, use VERILOG language, ISE13.2 compile environment
lcd
- 这是一个用verilog写的LED的控制代码，其中主要是利用状态机的形式实现的-This is a verilog the write LED control code, which is realized in the form of state machine
12864
- 用VHDL语言控制12864液晶产生心形图案的源代码。-Control using VHDL 12864 heart-shaped pattern generated source code.
state
- 实现对输入序列检测功能 1． 低电平异步复位 2． 检测序列特征为10010 3． 输出高电平，维持一个时钟周期 4． 数据序列一个时钟周期为一个数据态，时钟上升沿触发检测 -Detection of the input sequence to achieve 1. Low asynchronous reset 2. Detection sequence is characterized by 10010 3. High output, maintainin
key_debuouce
- veriolg 按键消抖的程序,可以写成模块，后面直接调用-verilog key debounce
24Bit_Spi
- 24位数据转化为SPI指令，注释详细，位宽可自行更改，适用于多位数据转化为串行数据，实测可用-For SPI instructions, detailed notes, bit width can be self change, applicable to a number of data conversion for the serial data can be measured 24 bit data transformation
tlc549driver
- 8位AD转换芯片tlc549的驱动代码-the code of eight bits AD conversion chip (tlc549)driver
clock
- 这是一个时钟功能的verilog程序，实现即时功能-it s a clock program(verilog)!,it may be useful to your study!
IIC
- 利用NIOS软核实现IIC总线协议上数据的传输，并在EEPROM上验证-NIOS soft-core data transmission on the IIC bus protocol, and verify the EEPROM
barrelshifter
- barrelshifter code in vhdl
CAM
- CAM is useful vhdl code to understand its architecture which helps to write any code
bakema
- eda平台，VHDL语言设计，设计一个巴克码发生器。-eda platform, VHDL language design, design a Barker code generator.