资源列表
VHDL-ADDER
- VHDL的N位加法器，非常的好用，经过仿真验证的！
fsm
- VHDL新手入门：有限状态机练习（三段式结构）-VHDL Getting Started: Finite state machine exercises (three-stage structure)
sram
- SRAM implementation source code in VHDL
jtd
- 交通灯vhdl程序，使用交通灯模块的 12个发光二极管，东西EW为主干道主干绿灯50秒，红灯30s，黄灯5s。-Vhdl program traffic lights, traffic lights use light-emitting diode module 12, East EW 50 seconds for the trunk main green, red 30s, yellow 5s.
Conversor_DAC
- conversor DAc SPTARTAN-3AN descrito en vhdl
TIMER_tb_v1
- testbench for the alarm clock circuit
taxi
- VHDL实现的出租车计价器,简单易行，能够完成基本的几家功能-VHDL source code for taxi meter
mealy FSM
- mealy fsm 和moore fsm-mealy Fsm and moore Fsm
fsk
- 用Verilog实现FSK调制，调用IP核实现正弦余弦的调制-Verilog implementation using FSK modulation, called IP core to achieve the modulation sine cosine
test_ad9852
- 使用FPGA来控制DDS信号的产生，从而达到高频信号产生的目的。使用的DDS芯片为AD9852，在QuartusII下编写。-Using the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. Use of DDS chip AD9852, in the QuartusII prepared.
interrupt_FSM_for_picoblaze
- finite state machine interupt handler for xilinx spartan 3E
rcv
- rs232 接受模块 处理 窜信号 分并信号-rs232 verliog receive module