资源列表
mc8051_vhdl
- mcs51的vhdl IP核,是每个学习FPGA的必经之路，希望一起探讨-mcs51 the vhdl IP core, each is a must to learn FPGA, hoping to explore together
MC8051
- VHDL版的C51核(MC8051)
Example-b4-2
- Altera IP应用设计实例 “\\Example-b4-2\\Project”目录下为设计工程 “\\Example-b4-2\\Solution”目录下为正确的解决方案，仅供读者参考
vga
- vga显示，可以用fpgavga连接显示器显示彩条，简单实用的verilog程序-vga display, you can connect with fpgavga display color bars, simple and practical procedure verilog
seg
- 六位十六位进制数可逆循环计数器、七段译码器设计，完全有VHDL语言设计，生成SYM文件后，设计top.gdf文件，赋好管脚下载到altera芯片上执行。-Sixteen decimal six reversible cycle counter, seven-segment decoder design, fully VHDL language design, build SYM files, design top.gdf file, assign a good pin downloaded to
eda
- 本实验目标是利用FPGA逻辑资源，编程设计实现一个串行通用异步收发器。实验器件为“创新综合实验平台”上集成的Altera NIOSII开发板，FPGA芯片型号为EP1C12F324C8。电路设计采用VHDL硬件描述语言编程实现，开发软件为QuartusII6.0。-The goal is to use the FPGA logic resources, programming design realize a serial general asynchronous transceiver. Th
VHDL
- VHDL语法学习PPT，非常简洁明了，重点突出。很有参考价值-VHDL grammar learning PPT, very concise and focused. Useful reference
SPI_IIC_design_example
- ALTERA原厂提供的例程，网上很难找到的，在MAX2系列芯片上实现过，VHDL和VERILOG两种语言编写 IIC读写程序-ALTERA provided the original routine, it is difficult to find online and in the MAX2 series chip-off, VHDL and VERILOG two languages
KEY_SCAN
- 矩阵键盘，八个键显示0~f，比在数码管上显示-Matrix keyboard, eight key show 0 ~ f, than in digital tube display
mc8051-IP
- VHDL 8051 IP, VHDL写的8051的IP核。-VHDL 8051 IP
test_vedio
- xilinx hdmi output yuv4:2:2 sd
vhdl_speedway_f07_9_2_2_0
- Introduction to VHDL about basic program-Introduction to VHDL about basic program..