资源列表
AteralIP.rar
- Altera IP核8B10B编码器的完整设计流程包括Altera IP的定制、仿真和实现的全过程,Altera IP core of the integrity of the 8B10B encoder design process, including the Altera IP customization, simulation and realization of the whole process of
xiaoyaundaling
- 这是一个利用ＶＨＤＬ语言编写的校园打铃系统，它具有正常数字钟功能，通过按键的操作可以实现时间的切换显示与调整，以及春夏与秋冬两季的打铃时间表的切换控制。-This is a campus using VHDL language ring a bell system, which has normal digital clock function, the operation can be achieved through the key switch time display and adjus
vhdl-implementation-of-cordic-algorithm-for-wirel
- OFDM system model and Block diagram of CORDIC algorithm using FPGA VHDL code -OFDM system model and Block diagram of CORDIC algorithm using FPGA VHDL code
00ic_Example
- 动态四位数码管显示程序，vhdl语言，对于数码管动态显示可以直接用。-display of daysic of seg-4,write with vhdl can use in fact
Altera_IP_verilog
- Altera IP的产生与实现。定制一个8B10B编码器，采用verilog语言建立仿真模型，并验证。-Altera IP generation and implementation. Customize a 8B10B encoder, using verilog language, a simulation model, and verify.
EDACLOCK
- 用VHDL语言编写数字钟的程序，实现数字钟的完整功能，如计时、校时、闹钟和整点报时-Digital clock using VHDL language programs, digital clock several functions, such as timing, timing, alarm and hourly chime
mySRAM
- VGA显示代码 分辨率为800x600 只要稍微改一下参数 可改变分辨率-VGA display code resolution for the 800 x600 as long as a little bit change the parameters can change resolution
docppt_9
- matlab使用手册，很有帮助作用的，对于查找函数。-matlab manual, helpful role, for the search function.
IIC
- IIC FPGA 代码 功能齐全 希望有需要的人下-IIC FPGA code is fully functional
VHDL
- VHDL 学习资料 PPT 文档 初学者非常不错的参考-VHDL learning data PPT document beginners a very good reference
Channel_Equalizer
- 使用Verilog编写的信道均衡器，可以有效解决抗多径问题，ISE12.2下编译通过-Written in Verilog channel equalizer can be an effective solution to anti-multipath, ISE12.2 compiled by
Design-of-traffic-lights
- 针对十字路*通信号灯的设计。开发工具为Quartus II 5.1。内含完整报告和可运行程序文件。功能非常好，可做学习参考。-For the design of the traffic lights at the crossroads. Development tools for the Quartus II 5.1. Containing the full report and run the program file. Very good, to do with learning refe