资源列表
SEGMENT_SCAN_CLOCK_24
- 設計VHDL24小時的時鐘，去除了按鍵彈跳現象-design VHDL24-hour clock, in addition to keys bouncing phenomenon
vhdl
- some of the basics of vhdl language
DDS-in-Verilog
- Verilog编写基于FPGA的DDS实现，内含源代码，希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
wishbone_VHDL.rar
- wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流,Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
GPS
- 本程序实现功能为接受GPS接收机时间信息，并编码形成IRIG-B时间码，同时跟设备总线通过485进行通信。包括原理图，单片机程序及CPLD程序。-This program implements functionality GPS receiver for receiving the time information, and encoding IRIG-B time code is formed, while with the device 485 to communicate via the
digital_second_clock
- 设计一块数字秒表，能够精确反映计时时间，并完成复位、计时功能。-Design a digital stopwatch, the time to accurately reflect the time and complete the reset, timing functions.
counts1
- 计时器 具有计到59分59秒自动停止不计的功能 可按键控制其状态 启动或停止计时器-The timer has plans to 59 points 59 seconds to be automatic stop regardless of the function of the key control state start or stop the timer
DAY07
- verilog 编写的查询法和线反转法举证键盘实例程序-verilog matrix—key
TurningKnobon-Spartan3E
- Let you control the 8 LED s on a spartan 3E board. Simple program to learn and understand VHDL
traffic_led
- 基于FPGA芯片设计多功能交通灯，该模块利用状态机设计，能实现交通指示功能-FPGA-based chip design multi-functional traffic lights, the module state machine design, traffic directions
Xilinx_pcie_DMA_S6_sim_tutorial6
- xilinx，spartan 6 DMA 仿真教程-Xilinx_pcie_DMA_S6，sim_tutorial4，DMA control
BEEP
- 电子产品世界网站的一个FPGA DIY的一个项目，这个是蜂鸣器的一个实例源码！-The electronics world website of a FPGA DIY project, this is an instance of the source code of the buzzer!