资源列表
pci-transmission-interface-design
- pci传输的接口设计的verilog，未用桥接芯片-pci transmission interface design verilog, unused bridge chip
stopwatch
- Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
13-v-12-A-P-photo
- switching power supplay 220 to 13.3 volt 12.5 A fscq1565rt-switching power supplay 220 to 13.3 volt 12.5 A fscq1565rt
game
- VHDL写的猜数字程序，首先随机出四位数字，依次猜测，给出几A几B作为参考（A是位置数字都对的，B是数字对位置不对的）-VHDL the write Caishuozi program, first four-digit random guess in turn given a few A few B as a reference (A position numbers are right, B is a number on the wrong place)
Demultiplexer
- The code of implementation of a demultiplexer. Very useful to understand of working principle of demultiplexers.
CORDIC
- 用VHDL语言，利用迭代移位算法cordic实现告诉加法功能 -Using VHDL language, using iterative shift algorithm to achieve told additive function cordic
RS-5-3-CODE
- RS(5,3）编码器原程序 程序已经调试过 且比较简短-RS(5,3） coder ,this code is very short
fpgashaizi
- 这是用FPGA实现的设计两人掷骰子比较点大小的游戏，里面有详细的程序源码及分析，希望有些帮助-This is the design with FPGA realizing compare two dice game, the size of the points are detailed in the program source and analysis, hope some help
2011-EDA-1
- 2011全国电子创新设计竞赛培训资料，第一手原创资料-EDA-Electronic Innovate Design
DE2_i2sound
- 这种设计将来自麦克风的音频输入信号线相结合，并把结果输出到输出信号线。将麦克风连接到MIC端口，一个音频源的LINE IN端口，扬声器/耳机的LINE OUT端口。-This design combines audio input from the microphone and line in signals and outputs the result to the line out signal. Connect a microphone to the MIC port, an audio
AES
- AES算法部分模块行位移列变换以及主题程序加密解密-AES algorithm transforms part of the module rows and columns relating to the displacement of encryption and decryption program
Comparator
- Verilog program for an 8bit up down counter