资源列表
VerilogHDL(8-10)
- verliog程序的教程和一些实例方便学习-verliog program tutorials and examples to facilitate learning
AT510-BU-98000-r0p0-00rel0
- CORTEX-M0处理器官方公开的源代码包！采用模糊网表生成，不可读但可综合可仿真可流片，还有testbench示例，很宝贵的资料！-CORTEX-M0 processor officially open source code package! Netlist generated by fuzzy, unreadable but comprehensive simulation can be taped, as well as testbench example, very valuable
stop_watch_with_doc
- vhdl code for stopwatch
61EDA_C1009
- vhdl step motor control
sdramc_vhdl
- Xilinx提供的SDRAM控制器参考设计（VHDL)-SDRAM controller reference design (VHDL) designed by Xilinx
88E1111_full
- 88E1111 千兆phy完整资料，如果做千兆应用可以看着个资料。 非常详细-88E1111 Gigabit phy complete information, if the application can be done looking at a Gigabit data. Very detailed
binary-squarer
- BINARARY SQURING CIRCUIT DOCUMENTATION
SGvga
- 基于System Generator 实现Xilinx FGPA的VGA显示模块，板块Nexys™ 3 Spartan-6 FPGA Board，可以直接把.bit文件下进去进行。 具体说明可以参考本人博客：http://www.openhw.org/wenlong0601/blog/12-03/239390_f7ef3.html-Based on the System Generator Xilinx FGPA VGA display module, the plate Nexy
class11_uart_tx
- verilog编写的串口发送程序，学习串口的话可以用作参考，已经实际验证过-Verilog prepared by the serial port to send procedures, learning serial port can be used as a reference, has actually verified
users-logic-for-Avalon
- SOPC Builder中用户逻辑如何接入Avalon总线？-how to link user s logic with alavon?
clock
- vhdl语言实现的时钟功能的quartus工程。在FPGA上运行可以得到时钟效果，并有调节功能。-vhdl language to achieve clock quartus project. Can get the clock running on the FPGA results, and regulatory function.
Oscillograph
- 在EP1C6Q240上实现示波器的逻辑代码.Verilog编写!很好用.调试成功.