资源列表
DE2_70_ControlPanel_V1.5.0
- this software is used to load pictures into sdram
NiosIIUCOSII
- NIOSii移植uCOSII系统的指导教程，对于初学者，很有指导价值，-NIOSii transplantation uCOSII guidance system tutorial for beginners, useful guidance value,
timing_sim
- 使用ModelSim对Altera设计进行时序仿真的简单操作步骤-Simple operation steps using the ModelSim timing simulation for Altera design
Harrisp20pdf2
- DIGITAL BUILDING BLOCK
4x4-Keypad
- 基于FPGA EP3C16芯片的4X4键盘程序，已测试通过，使用Verilogy语言编写，引脚已配备-4X4 keyboard program based FPGA EP3C16 chip have been tested by use Verilogy language, have been equipped with pin
led_ysd
- 在quartusII下开发的八段码的verilog程序，方便大家的学习-In eight out quartusII developed under the code verilog program, we facilitate the learning
NAVI
- 基于fpga的GPS导航数据发生器，使用verilog编写- Fpga-based GPS navigation data generator, using verilog write
gvhdl
- 近百个vhdl的器件编程,虽然个别较为简单,但都很实用,对于初学者会有很大帮助-Device close to a hundred VHDL programming, although the individual is more simple, but very useful, would be of considerable help for beginners
Magic-Gloves-master
- 魔法手套主工程文件VERILOG语言，蛮不错的-Magic glove main project file VERILOG language, pretty good! ! !
music
- 各种音乐播放的小程序，对学习FPGA学习的音乐播放有一定的帮助。-Applet variety of music playback, music player to learn FPGA learning some help.
CPU
- 实现了简单的CPU功能 采用三级流水线和超标量-CPU functions to achieve a simple three-stage pipeline and superscalar
vhdl
- Very high speed integrated Hardware Descr iption Language (VHDL) -是IEEE,工业标准硬件描述语言 -用语言的方式而非图形等方式描述硬件电路 容易修改 容易保存 -特别适合于设计的电路有: 复杂组合逻辑电路,如: -译码器,编码器,加减法器,多路选择器,地址译码 -Very high speed integrated Hardware Descr iption Language (VHDL)-