资源列表
UART_REF
- 使用VHDL语言编写的UART IP code, 有完整的SIMULATION-uart IP code with vhdl
ds769_axi_slave_burst
- xilinx AXI4 slave burst 接口的介绍文档，有助于理解IP核-The introduction of xilinx AXI4 slave into the interface documentation
sync-and-asyn_FIFO_verilog
- 同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references
verilog-HDL
- verilog hdl使用教程，详细入微的讲解了FPGA开发的必备工具verilog HDL语言。对于新手入门有很大的帮助。-verilog hdl use of tutorials, detailed explanations of the FPGA nuanced development of the necessary tools verilog HDL language. For beginners a great help.
crc16_finished
- 使用Quartus II软件开发，编程语言为Verilog，实现的是FPGA源代码-Using the Quartus II software development, programming languages Verilog, FPGA source code to achieve the
XPS_Custom_IP_Tutorial
- Tutorial to create a custom AXI based IP for Xilinx
FPGA-TLC5620
- 基于FPGA的线性序列机与串行接口DAC驱动设计-Design of DAC driver for linear sequence machine and serial interface based on FPGA
fpgacy7c68013
- fpga 与usb 芯片cy7c68013的doc文档，用的是slavefifo方式-fpga with usb chip cy7c68013 the doc file, using slavefifo way
DDS-STC89C52-DAC0800-FPGA.doc
- 电子设计大赛，波形发生器，基于单片机和FPGA的DDS信号源。-Electronic Design Contest, waveform generator, microcontroller and FPGA-based DDS signal source.
fpga_dds_coylone_2
- dds设计，花了一个星期做的,verilog写的，可生成多种波形，频率范围可上M,性能不错。-dds design, spent a week doing, verilog to write, can generate a variety of waveforms, the frequency range available on the M, the performance good.
clock_18b20
- 基于lcd1602的温度计和数字时钟,包含详细的代码解释和实现方式-Lcd1602 based thermometers and digital clock
ser_in_per_out
- 串入并出寄存器，很好很强大。使用Verilog进行设计并用Modelsim成功仿真。-String into register, very very strong. With Verilog for design and simulation using Modelsim successfully.