资源列表
std_logic_unsigned
- 一组符号arithemtic、转换,并比较STD_LOGIC_VECTOR功能的程序包。-A set of unsigned arithemtic, conversion, and comparision functions for STD_LOGIC_VECTOR.
vhdl
- 交通灯控制 频率计case when语句 vhdl硬件描述语言编写-Vhdl traffic light control hardware descr iption language of transformation to achieve control of traffic lights
IIC_NIOSII
- 基于NIOS II软核的IIC（模拟I/O口）总线驱动程序-NIOS II soft-core based on the IIC (analog I/O port) bus driver
Alu1232
- VHDL开发的计数器。源程序不复杂，应该都能看懂。最重要的注意：是时序问题-VHDL development of the counter. Source code is not complicated, should be able to understand. The most important Note : Timing is the issue
miller
- miller码编码模块的verilog程序，修正miller码编码模块的程序，完成miller码编码模块功能。-miller module verilog coding procedures, the amendment procedures miller coding module to complete the miller coding module function.
checkoutthedate
- 该程序的功能是用来查询日期或是知道日期查询星期几的；-The program' s function is used to check the date or the date of check to know a few of weeks
7Segment2bcd8bit
- vhdl seve segment to bcd 8 bit
shuzipinlvjiVHDL
- 功能：频率计。具有4位显示，能自动根据7位十进制计数的结果，自动选择有效数据的 --高4位进行动态显示。小数点表示是千位，即KHz-Features: frequency meter. With four shows that will automatically count 7 the results of the metric system to automatically select a valid data - 4 high-dynamic show.
F_ADD
- 使用硬體描述語言verilog的運算單元-it s an ALU using verilog to design
Divider
- 一个除法器的FPGA代码设计 Divider-fpga Divider
FIR
- 数字滤波器，可以从外部接口更改参数，方便修改-The digital filter can change the parameters the external interface, easy to modify
自动售货机
- 先投入一定数目货币，然后根据货币购买力进行相应货物的选择，然后确定购买，出货并找零，完成交易。也可在确定购买前任何时刻按取消键退出所有货币。