资源列表
digital
- 多功能数字钟的VHDL源代码。多功能数字钟具有的功能：显示时－分－秒、整点报时、小时和分钟可调等基本功能。钟表的工作是在1Hz信号的作用下进行，每来一个时钟信号，秒增加1秒，当秒从59秒跳转到00秒时，分钟增加1分，同时当分钟从59分跳转到00分时，小时增加1小时。-Multifunction digital clock VHDL source code. Multi-function digital clock with functions: display- minutes- seconds
ADS7864
- 基于quartus的FPGA ADS7864的AD采集。-the ad conver ic is ADS7864 use fpga
ps2_key
- 实现通过PS/2接收键盘的数据，然后将输入的大写字母转化成ASCII，通过串口传送给PC机。-Achieved through the PS/2 keyboard to receive data, and then enter the uppercase letters into ASCII, transferred to the PC via the serial port.
key_master_0621
- 关于4*4矩阵键盘扫描电路verilog代码设计，支持Avalon总线-On the 4* 4 matrix keyboard scanning circuit verilog code design, support Avalon bus
floating-point-adder
- verilog implementation of the floating point adder
spigpio
- spi接口转GPIO，比较简单好用，可以看一下-spi interface switch GPIO, relatively easy to use, you can look at
FF_CTRL
- 简单实用的FIR notch 滤波实用，可以直接使用。 y(n) = 0.5*x(n) - 0.5*x(n-m)-simple FIR notch filter,y(n) = 0.5*x(n)- 0.5*x(n-m)
fpdpsk
- FSK/PSK信号调制器的VHDL程序，共分为分频器、m序列产生器、跳变检测、2:1数据选择器、正弦波信号产生器和DAC(数、模变换器)6部分-FSK/PSK signal modulator VHDL program is divided into divider, m sequence generator, transition detection, 2:1 data selector, the sine wave signal generator and DAC (number, mode
hdb3_1.1
- verilog 语言hdb 3 编 码 经过测试，但冗余问题未解决-Verilog language coding hdb 3 tested, but unresolved questions redundancy
cf_fft_256_8
- This is a source code of 256 point fft architecture. This code is also available with opencores-This is a source code of 256 point fft architecture. This code is also available with opencores
N_C
- Medium module for calcilating Modular Multiplication by Montgomery algorithm. q = (x0 + ai*b0)*m_sh. It calculate m_sh. For it it need the LSB byte of module. My E-mail: suhrob106@rambler.ru
sipo_vhd.zip
- serial in parallel out using vhdl,serial in parallel out using vhdl