资源列表
WashingMachine
- 洗衣机系统，用VHDL硬件描述语言编程实现洗衣机控制电路。要求实现如下功能： 1.拨动电源开关，洗衣机电路进入工作状态，默认为标准洗涤程序 2.按下启动/暂停键，洗衣机开始按照既定程序工作，再按下该键，洗衣机暂停 3.洗衣机工作模式可以选择 4.洗衣机水位可以选择 每按下一个按钮，洗衣机发出“嘟嘟”警报 -Washing system, using VHDL hardware descr iption language programming washing machin
divider8
- 这是一个8分频器，可以将输进来的信号进行8分频后输出-This is a 8 frequency divider which can transfer the input clock signal into 1/8 clock
lcd_drv
- IP core for LCD controller of Xilinx FPGA
shixuzhuangtaiji
- verolog语言编写，功能如标题所示。有问题请联系mxkmxm@126.com-verolog language, functions such as the title indicates. There are problems, please contact mxkmxm@126.com
sd_card_test
- 基于fpga的sopc系统的sd卡调试程序-System based on fpga s sopc debugger sd card
classic
- Verilog源码，完成数据转换，供学习使用！
LCD_Test
- 液晶测试,已可以作为最终版本(能稳定驱动本类型的任何LCD屏)-LCD Test
Fuzzy_PID
- 用VHDL语言编写的模糊PID程序代码。成功调试，运行良好。-The source code of Fuzzy_pid in VHDL.Simulation was successful.
histogram-equalization-verilog
- 直方图均衡的Verilog实现 从Matlab读出图像为image.txt文件，经过Modelsim读入TXT文件进行直方图均衡处理，将输出结果再读出为image_he.txt文件，然后在Matlab观察直方图均衡增强效果。-The histogram equalization Verilog read from Matlab the image image.txt file after the Modelsim read into the TXT file, histogram equaliz
acdcx
- 在LCD液晶屏上显示自己的名字，并带有滚动效果-Own name, and displayed on the LCD screen with a scrolling effect
top_net_8b10b
- Lattice Semiconductor 8b10b-Lattice Semiconductor, 8b10b
project5_UART
- It is UART protocol in VHDL. it has two files. one is transmitter and one is receiver.