资源列表
EPD
- Quartus II开发环境下的鉴相器的图形实现。-Quartus II phase discriminator
VHDLSourceProgramofVGAOut
- 彩条信号显示的VHDL源程序，了解VGA现实原理，理解各个VGA控制信号的作用。-VHDL Source Program of VGAOut
NIOS_Uart
- 基于NIOS，串口---RS485通讯程序。接收中断函数的注册用服务。-Based on NIOS,--- RS485 serial communication program. Receive interrupt function registered with the service.
simple_function
- This a rc5 encryption simple function code. Note that keys here are already been selected. You can add a vhdl code for key generation is well.-This is a rc5 encryption simple function code. Note that keys here are already been selected. You can add a
FIFO
- 一个用VHDL源码编写的先进先出(FIFO)缓冲器模块.可以进行FIFO的仿真验证-A source prepared by VHDL FIFO (FIFO) buffer module. Can verify FIFO simulation
lcd_controlveriloghdl
- 使用Ｖeriolog hdl 编写手机屏测试程序．-Veriolog hdl prepared to use cell phone screen test.
EDGELAP
- Based on this one-dimensional analysis, the theory can be carried over to two-dimensions as long as there is an accurate approximation to calculate the derivative of a two-dimensional image. The Sobel operator performs a 2-D spatial gradient measurem
ECHO_DE2
- Very good info. for RS-232 echo VHDL code .
QAM
- 16qam调制器的FPGA实现。使用Verilog实现全数字16-QAM调制器。-16qam Modulator FPGA. Use Verilog for full digital 16-QAM modulator.
2wireKeypad
- ks 0108 graphic lcd header
play_bench
- 用于对ACE JTAG Player设计的IP核文件进行测试和检验-Testing and inspection for the ACE JTAG Player IP core design files
MyFilter.rar
- FPGA实现数字滤波器，用VHDL语言实现的直接1型FIR滤波器，具有较好的参考价值。,FPGA realization of digital filters using VHDL language to achieve the direct FIR filter type 1, has a good reference value.