资源列表
OneD_DCT8
- 一维DCT变换，使用Verilog ＨＤＬ语言实现。有ＳＹｎｐｌｉｆｙ编译脚本-One-dimensional DCT, using the Verilog HDL language to achieve. The SYnplify compiled scr ipt
240128
- 240128驱动，验证已通过，驱动芯片6963的12864-240128 device
lcd
- 改VHDL程序通过简单算法实现 宫殿显示 可供初学者参考，极有价值！-VHDL procedures changed through a simple algorithm for beginners palace show reference, very valuable!
user_logic_SEG7_LUT_8
- freeDev数字应用开发板中的七段数码管的IP核的verilog实现-freeDev digital application development boards in the seven-segment digital tube of the IP core implementation of the verilog
TLC5615_Verilogprogram
- TLC5616的控制和驱动程序，通过一个顶层文件建立连接，编写了一个Modelsim上的仿真测试用例，仿真结果正确。-TLC5616 control and driver, through a top-level file to establish the connection, the preparation of a simulation test case on the Modelsim, the simulation results are correct.
seg
- 一个时钟程序，还有跑表，感觉相当不错的，有需要就下载吧
LCD
- its a sample code of using keyboard and lcd on fpga evulation board.
clock
- 两个按键控制校时的VHDL时钟源码，带定时闹钟和日历功能
clock
- 用高速硬件语言VHDL设计的全功能数字钟，经测试运行稳定-VHDL language used high-speed hardware design full-function digital clock, tested and stable operation
Electronic-clock
- 用VHDL语言实现一个24进制的电子时钟，其中设置一些按键改变数值等-VHDL language with a 24-band electronic clock, which set up some key changes in values, etc.
verilog-HDL--LCD-display-
- 用verilog HDL 实现LCD显示-using verilog HDL to LCD display