资源列表
VHDL
- 分块地址产生电路，根据FPGA的要求，按照存储模块分块管理的要求产生电路-Block address generating circuit according to the requirements of FPGA, the memory module according to the requirements of the management block generating circuit
fpgacaiji
- 自己课程设计写的程序，用FPGA控制ADC0809的转换时序来完成模/数转换，然后将转换完的数字信号传递给0832-write their own curriculum design process, Connection between ADC 0809 FPGA control the timing to complete the conversion analog / digital conversion, End then converting the digital signal to
sdram
- 用verilog语言编程实现的SDRAM模块，可用于配置在FPGA中-Verilog language programming with the SDRAM module, can be used to configure the FPGA,
run time expandable cache
- Expandable cache proposed by Bournoutian and Orailoglu is very efficient in reducing miss rate and energy consumption with small area overhead. However, the original expandable cache with only one expansion scheme may lead to thrashing problems. In t
manchester
- A simple Manchester Encoder to convert serial data to Manchester encoded data.
AdcInterfaces
- A VHDL Code For ADC Interfaces
PCI_BUS_Verilog
- PCI_bus_Verilog example
design-digital-clock-using-vhdl
- digital clock code document using vhdl code. have to test it once.
channel_fir
- 用于无线通信数字基带的信道选择滤波器，verilog代码-Used for wireless digital baseband channel selection filter, verilog code
hdl.rar
- 双向RAM控制程序,使用VRILOG HDL 编写，简单实用,DAUL RAM control
uart-vhdl
- 不错的uart总线程序，已经测试过，没有问题啊-Good uart bus program, has been tested, there is no problem ah
hanshushengchengqi
- 实现函数生成，可以对比参照着这个程序进行修改，是一个很好的参照实例-Function generation, can be cross-referenced with the program to be modified is a good reference instance