资源列表
add_ff8
- FPGA adder code flip-flop verilog code -FPGA adder code flip-flop verilog code
watch
- 用FPGA实现带马表日历的电子表，verilog代码。
i2c_master_top
- i2c core : i2c master top
counter
- counters varyin from 6,10,12
lingmindu
- 心电图机中灵敏度控制的VHDL代码，想交流的加我QQ147440013
qingdaqi
- 四路抢答器，超时报警，提前抢答报警，计分等-Answer four, and overtime alarm, warning in advance Answer, including classification
clock
- 数字中的vhdl程序，功能包括正点报时，定时和倒计时功能，并可以发出声音。-Number of vhdl program features include punctual timekeeping, timing and countdown function, and can sound.
test
- 文思公司的测试习题，想进入文思公司当测试工程师的，可以拿来看看。-Evans' s test exercises, the company wanted to enter Evans when the test engineer can be used to see.
VHDL
- 时钟发生器用于生成不同的时钟信号clock、clk2、fetch与alu_clk，产生的时钟信号clk送往寄存器与状态控制器，时钟信号clk2送往数据控制器与状态控制器，信号fetch送往数据控制器与地址多路器，信号alu_clk送往算术逻辑单元。-Clock generator to generate different clock signals clock, clk2, fetch and alu_clk, generated clock signal sent to register w
UART_EX
- Uart 232 module example divied by 3 module.
sdram_basemod
- 可以实现sdram的页读写功能，其中加了两个FIFO缓冲器，只需稍改就可以加入工程。-Sdram page can read and write capabilities, including the addition of two FIFO buffers, just a little change can join the project.
min_max_finder_part1
- 最大最小值寻找程序，可以实现自动查找最大值与最小值-min_max_finder