资源列表
Mux32to1
- mux 32 to 1 verilog code. It may be good for you !
shuzhiDDS
- 基于FPGA器件、采用VHDL语言的数字频率计，-Based on FPGA devices, the use of VHDL, digital frequency meter,
aurora_1_example
- serial communication using aurora core
DE1_D5M
- // --- --- --- --- --- --- --- --- --- --- --- -- // Copyright (c) 2007 by Terasic Technologies Inc. // -------------------------------------------------------------------- // // Permission: // // Terasic grants permission to use and mod
randwofram
- read and write operations of ram in vhdl
CPLD_i2ccontroller
- AD9985的i2c控制器，verilog代码-the Verilog IIC controller for AD9985
SourceFile
- PS2键盘实验Verilog HDL代码
Traffic-control-program
- 交通灯的控制程序-Control program for traffic light........
QAM_verilog
- 基于FPGA的16QAM，用verilog编写，其中DDS为自己编写，含设计文件和testbench。已通过moldesim软件仿真。 -FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.
6
- 4位数码扫描显示电路,我们控制一个七段LED需要8个输出端口；如果要输出四位十进制数，就需要32的输出端口，这将占用大量的端口资源。采用串行扫描显示，我们只需要8+4共12个端口即可。其原理是：用一个四位的输出端控制，某一时刻只选中其中的一个LED（输出为‘1’表示选中），八位的输出端将该LED所需要显示的值输出；然后四位的输出端值改变，选中下一个LED。这样依次类推。如果选择的频率很快，达到50Hz以上，由于人眼的视觉暂留效应，看起来就像4个LED同时显示。 设计一个程序，输入四个一位十
jishuqi
- 一个9999的计数器，然后用4个数码管显示当前数值，数码管共用a到g口，通过com1到com4选通的- 9999 counters, then with 4 nixietube demonstration current value, the nixietube use in common a to g, through com1 to the com4 selection
pmw2ppm
- Vhdl code PPM to pwm converte