资源列表
clockprj
- vhdl实现的万年历代码，年月日 星期 闹钟功能、-vhdl to calendar code, date week alarm clock function,
sourcecode
- 《FPGA嵌入式项目开发三位一体实战精讲》一书的程序代码-The FPGA embedded project development trinity combat succinctly book code
m-xulie
- 频率可步进M序列发生器 从10K 到100K ,步进为10K VERILOG编写-M-sequence generator frequency step from 10K to 100K, the preparation step for the 10K VERILOG
piplelinecpu
- 流水线CPU，实现MIPS简单指令的运行，在XLINX实验板上运行-Pipelined CPU, MIPS simple instructions to achieve the operation, run in XLINX experimental board
RTThread_uart1
- RTSTREAD实现功能: 利用通用定时器实现定时加一-RTSTREAD functions: the use of general-purpose timers to achieve timing plus a
caiji_tij
- nios2 example study useful nios2 example study useful nios2 example study useful-nios2 example study useful nios2 example study usefulnios2 example study usefulnios2 example study useful
8051_latest
- this project is regarding 8051 microcontroller development in VHDL language using xilinx tool for synthesis of code-this project is regarding 8051 microcontroller development in VHDL language using xilinx tool for synthesis of code
FPGA-Read-or-Write-CF
- 利用ALTERA FPGA实现对CF的读写操作-Using ALTERA FPGA implementation of CF, speaking, reading and writing operations
cordic3
- 利用cordic计算三角函数的verilog程序和modelsim仿真-To use cordic calculated trigonometric verilog program and simulation
dds
- dds算法，调用xilinx IP ，ise(DDS algorithm, call Xilinx IP, ISE)
24_lcd_gui
- 这个是我从黑金社区上找过来的 是关于LDC/GUI系统设计的代码 希望对大家学习FPGA有用-This is I can come the black community is on the LDC/GUI system design code, we hope to learn useful FPGA
4BITMCUVERILOG
- 4位软和设计，用的是FPGA语言，已经成功应用-4 soft design, using FPGA language, has been successfully applied