资源列表
fifo_vhd
- vhdl编写的fifo程序-VHDL procedures prepared by the fifo
gray_binary_conv
- 用VHDL实现的格雷码，有格雷码计数器、格雷码转二进制、二进制转格雷码！-VHDL implementation of the Gray code, there is Gray code counter, Gray code to binary, Gray code Binary!
Pulse
- 脉冲*生器,用于产生激励的触发脉冲群，也可用于干扰脉冲群产生-Burst generator, for generating a trigger pulse excitation group can also be used to generate the noise burst
CFO
- zedboard/AD9361平台进行无线收发，在接收端进行频偏估计和补偿的Verilog参考代码。-zedboard/AD9361 platform for wireless transceiver, the receiver frequency offset estimation and compensation, you can refer to the Verilog code.
流水灯VHDL程序
- 流水灯的VHDL原程序,以4种模式LED显示.-wasted lights VHDL program, in the four-mode LED display.
SPI_verilog_mycode
- 基于Verilog HDL的SPI代码，可在FPGA上实现SPI接口，请大家参考-Verilog HDL based on the SPI code, implementation in FPGA on SPI interface, please refer to
div_frequency
- 任意分频器，用Verilog HDL实现，只需修改参数可以实现奇数、偶数分频，FPGA应用必备资料。-Any divider, using Verilog HDL to achieve, simply modify the parameters can be achieved odd, even frequency, FPGA applications necessary information.
VHDL-test-code-8-bit-shift-register
- VHDL实验代码：8位移位寄存器，这是一个基于VHDL的8位寄存器，非常实用的一个小程序-VHDL test code: 8-bit shift register, which is a VHDL-based 8-bit registers, a very useful little program
1602LCD
- Arduino中关于1602 LCD显示的演示程序。-The code of LCD playing demo about arduino
FIFO_altera.v
- FIFO for Altera Cyclone II or Cyclone III on memory blocks. Length of FIFO can be changed.
AD_TLC549
- FPGA控制AD芯片TLC549采集信号，-TLC549 AD chip FPGA control signal acquisition,
cic3s32
- 一个3阶的32位抽取的cic滤波器的verilog源代码