资源列表
lab9_0~60
- 顯示0~60的循環數,可顯示在SEG上方!-Showing 0 to 60 cycles, SEG can be displayed in the top!
TXD_2
- TxD with ROM transmitter
frequency
- 8位十进制数字频率计的底层设计VHDL程序-8-bit decimal underlying design of digital frequency meter VHDL program
Pseudo-random
- 伪随机序列FPGA应用设计代码 Pseudo-random sequence-Pseudo-random sequence of application design
uartrx
- FPGA的verilog uart 接收端程序。非常实用-The FPGA verilog uart receiving end procedures. Very practical
dwt_32
- Haar wavelet for an image of 32*32.
AD0804_control
- 配置AD0804的VHDL代码，经过验证可参考学习-Configure AD0804 VHDL code, reference study validated
par_serial-and-serial_par-VHDL
- 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用,String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
XILINX
- Verilog汇编很牛叉 O(∩_∩)O哈哈哈~-Verilog
caideng
- 彩灯控制器，彩灯（LED管）能连续发出四种以上不同的显示形式；随着彩灯显示图案的变化，发出不同的音响声。 -Lantern controller, lights (LED tube) can be continuously sent more than four different display forms with the lantern display patterns change, make different audio sound.
Corrector_PZU_Correct
- hamming coder corrector
qd
- 数字抢答器的VHDL设计代码 数字抢答器的VHDL设计代码-The VHDL design of digital Responder Responder of the VHDL code for design of digital code