资源列表
MFSK
- 基于VHDL硬件描述语言，完成对基带信号的MFSK调制,源码
TEST7
- 这是一个键盘扫描的程序 没有去抖电路 但是还是很好用的 我测试过 很好用的-This is a keyboard scanning procedure did not go to shake or a good circuit but I tested used a very good use
statemachinecontroller
- it is a vhdl code for a state machine controller
syn_fifo
- 很好的同步FIFO设计代码，和大家分享一下，多多交流，不是我自己写的-Good synchronous FIFO design code, and share with you some more exchanges, not my own writing
fet440_uart01_09600
- MSP430 設定UART鮑率為96-UART MSP430
gen_act
- Verilog 语言下的 产生ACTIVE信号代码，即讲一段低电平信号转换为闪烁的信号-ACTIVE signal generated code under the Verilog language that speaks for some low-level signal is converted to a flashing signal
pipeline
- 简单的流水线的实现机制，基于verilog语言。-The pipelined implementation, based on Verilog language.
xor4b
- 四为异或门，实现全加器的硬件模块，使用VHDL语言实现，主要适用于初学者实例展示，为初学者提供quartus的实例展示。-4 bits xor gate finished with VHDL language， specifically for greenhands and bachelors who just begin with quartus
vote7-2
- 七人表决器 在表决的过程中 多于四个通过 少于四个不通过
ff_mul
- 伽勒华域乘法器用于RS编码中，用verilogHDL语言实现-Galle Hua domain multiplier for RS encoding, the implementation language used verilogHDL
fifo
- 格雷码对地址编码的异步FIFO的实现方法-Gray code encoding to address the realization of the asynchronous FIFO method
trafficlights
- 基于verilog的交通灯实现，红绿灯交替转换，在规定的时间内，可以人为控制！-Verilog implementation based on the traffic lights, traffic lights turn conversion, within a specified time, you can artificially control!