资源列表
ppscode
- verilog代码，输出秒脉冲，用于采集同步-verilog code, second pulse output for synchronization acquisition
ex_2
- FPGA 代码,可以作为练习VIVADO的使用于学习- CS_r[0] < CS CS_r[1] < CS_r[0] wrreq_r[0] < wrreq wrreq_r[1] < wrreq_r[0] READ_sig_old[0] < READ_sig READ_sig_old[1] < READ_sig_ol
FINAL_CODE_CAM
- this is a VHDL code for content address memory
DDS
- 基于FPGA，Verilog语言编写的DDS信号发生器，可生成方波、正玄波，三角波。-Based FPGA, Verilog language DDS signal generator that generates a square wave, sine wave, triangle wave.
FPGA_Projects_100
- FPGA_Projects_100，例程100例经典程序-FPGA examples
setmin_sec
- 用QuartusII13.0软件，DE1开发板实现的时钟程序，可设定的时间-With QuartusII13.0 software, DE1 development board to achieve the clock procedures can be set up time
huxideng
- 用Quartus软件，DE1开发板实现的呼吸灯，Led先由亮逐渐变暗，再由暗逐渐变亮-With the Quartus software, DE1 development board to achieve the breathing light, Led the first light gradually dimmed, and then gradually brightened by the dark
ping_pong2LED
- 用QuartusII13.0软件，DE1开发板，支持VGA的显示屏实现的乒乓球游戏，同时可实现七段数码管计分，球碰撞声等功能-With QuartusII13.0 software, DE1 development board that supports VGA screen realization of table tennis game, while achieving seven-segment LED scoring, ball impact sound, and other funct
ring_fifo
- use Sram with ring fifo Spartan-3
802.1as
- 802.1as gptp标准包解析verilog模块。用于实现EAVB协议的重要部分。-802.1as gptp verilog module, part of EAVB procotol
ADI_HDMI
- 从FPGA输出到HDMI Tx的verilog 模块。实现完整HDMI图像输出功能。-FPGA output to HDMI Tx module in verilog
EEPROM
- EEPROM verilog仿真模块,用于测试I2C接口-EEPROM verilog simulation module