资源列表
VGA
- Verilog实现VGA 6408480@60(Hz)-Verilog implements VGA 6408480@60(Hz)
SV-Combinational-Logic
- system Verilog combinational logic
SV-Priority
- system Verilog priority
SV-Tasks-a-Functions-Intro
- system Verilog tasks & functions introduction
SystemVerilog_3.1a
- system Verilog language reference manual
ALU_VERILOG_COCOTB
- ALU written in Verilog HDL and tester written in python using the cocotb library
SingleCycle8bitProcessor
- Simple 8-bit Single Cycle Processor in Verilog HDL
defuzzification
- fuzzification
fuzzy_rulebase
- fuzzy rulebase
traffic-light-FPGA
- FPGA做的路*通灯的完整实验，得到了全班最高95分，讲解详细，附工程文件，手把手教您-FPGA do traffic lights at the junction of the complete experiment, the class was up to 95 points, explain in detail, with engineering documents
uart_test
- altra fpga nios 开发uart工程-UART IP and test on nios
fir_csd
- vdhl实现FIR，乘法器采用CSD编码，在资源紧张情况下，可省去很多资源-vdhl achieve FIR, multiplier using CSD coding, in the case of resource constraints, can save a lot of resources