资源列表
lab16
- verilog HDL，秒表设计,数字系统设计实验-verilog HDL，design a watch, digital system design
ic_synthesis_based_ARM_lectures
- ic synthesis based ARM lectures
sigma-delta-modulator
- 实现SIGMA-DELTA Modulator的veriolog代码-sigma-delta moudulator for RFPLL
uart_rx
- 基于verilog的uart接收模块，16倍波特率采样，具有可选择奇偶校验功能，仿真成功。-Based verilog the uart receiver module, sampling 16 times the baud rate, parity function with selectable, successful simulation.
uart_tx
- 基于verilog的uart发送模块，具有可选择的奇偶校验功能，经过modelsim仿真可用。-Based on the uart verilog transmit module with selectable parity function, available through modelsim simulation.
xilinx_pcie_core_data
- XILINX PCIe核的文档说明及应用策略，文档有笔记，重点地方有注释标记，希望对初学者有帮助！-xilinx pcie core document and application strategy.and in the pdfs,there are notes after reading.
vhdl
- vhdl program vhdl programs with result device summary
convolution
- Source code for convolution of two complex number is written in Verilog language
encoder
- The code for 8 to 3 encoder is written in Verilog language.
divider1-(3)
- Code for divider is written in Verilog where divider and dividend both are of 8 bits. Division is done using continuous subtraction method until the divisor becomes greater or equal to dividend.
ZedBoardyuanlitu
- zedboard原理图详细，PCB板焊接方便，每个接口表明清楚。-Zedboard schematic in detail, PCB board welding is convenient, each interface that clearly.
VERILOG1
- 基于FPGA的cordic算法的verilog初步实现,可以学习学习，其中也有程序解释。-FPGA based on the CORDIC algorithm Verilog initial implementation, you can learn to learn, which also has a program to explain.