资源列表
fir25
- 用VDHL写的25阶对称FIR滤波器，在塞克隆3FPGA下验证没有问题（AD采样时钟50Mhz，这个对硬件设计有点要求），里面调用官方乘法器API，要节省资源可以采用CSD编码转换乘法器，可以减少一半以上的资源-VDHL written by a 25th order symmetric FIR filter in Seke Long 3FPGA under verify that no problem (AD sampling clock 50Mhz, this design is a bit
Lab4
- RAM design Objectives 1. Working with generic units. 2. Working with Arrays 3. Working with integers
Lab3
- Sequential binary Message detector Objectives 1. Working with finite state machines. 2. Defining user types in VHDL
Lab2
- Simple ALU Objectives 1. Explore simple ALU structure. 2. Working with components 3. Working with language templates in ModelSim 4. Making a test bench and simulation using ModelSim
Lab-1
- Design and simulate D flip flop with reset button. Objectives Explore Modelsim through a simple circuit design.
scrambler
- Verilog编写的ADC加扰程序（scrambler）里边附有加扰器的说明，实验可以把数据打散，可自行写testbench测试-Verilog prepared by the ADC scrambled program (scrambler) inside with scrambler descr iption, experimental data can be broken up, write their own testbench test
Buf_FiFo
- verilog 编写的FIFO，里边有IP核和控制模块，-verilog write FIFO, inside the IP core and control module,
testadcom
- XILINX FPGA模拟量采样通信测试 XC6SLX9完成AD采样通过光纤通信上传给XILINX XC6SLX25。-XILINX FPGA XC6SLX9 XC6SLX25
AX301
- 10个在黑金AX301开发板上实现的程序源码工程，程序烧进板子就可使用 内附word详细说明了各个工程功能-10 in the black gold AX301 development board to achieve the program source program, the program can be burned into the board Included in the word a detailed descr iption of the various enginee
DS1302
- 基于板载DS1302的电子时钟设计 AX301开发板上配置了一片实时时钟（RTC）芯片，型号DS1302。学习和掌握DS1302的基本原理，并完成电子时钟的设计。 要求：（1）用数码管显示时，分，秒； （2）有时间预置功能；-Design of Electronic Clock Based on Onboard DS1302 AX301 development board is equipped with a real-time clock (RTC) chip, model
DDS
- 信号发生器设计 信号发生器由波形选择开关控制波形的输出, 分别能输出正弦波、方波和三角波三种波形, 波形的周期为2秒（由40M有源晶振分频控制）。考虑程序的容量,每种波形在一个周期内均取16个取样点,每个样点数据是8位(数值范围:00000000~11111111)。要求将D/A变换前的8位二进制数据（以十进制方式）输出到数码管动态演示出来。-Signal generator design The signal generator is controlled by waveform se
clock
- 数字时钟设计 设计一个数字时钟 要求:(1)用数码管显示时/分/秒 (2)有时间预置功能 (3)能用蜂鸣器报时-Digital Clock Design Design a digital clock Requirements: (1) with the digital display hours/minutes/seconds (2) has the time preset function