资源列表
bujindianji
- FPGA实现步进电机控制源代码。通过脉冲信号控制，产生一定频率脉冲的信号（脉冲频率用来控制速度），经过信号隔离放大（达到驱动电机的电压）来驱动控制步进电机-FPGA Implementation of stepper motor control source code. Controlled by the pulse signal, generating a frequency pulse signal (pulse frequency is used to control speed), vi
syn_fifo_style_1
- verilog实现的，异步FIFO。所有代码在一个模块中。-verilog achieve, asynchronous FIFO. All code in a module.
LCD_BY_CPLD
- LCD Interfacing Code using CPLD
tb_contrast_stretch
- contrast strech for image pixles
hello
- fpga单片机入门第一步通过按键点亮第一个小灯-The fpga single-chip machine enters the first step by pressing the key to light the first light
husw
- 用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
half_adder
- half adder with testbench
jishuqi
- 各式计数器代码，从十五到六的各式计数器，方便大家参考，一看多用-Counter all kinds of code, from 15 to six kinds of counters to facilitate reference, see more ~ ~ ~
mqst
- 用Verilog HDL编程实现曼切斯特编码器的功能，程序结构简单，仿真后波形延时这方面也进行了相关的优化-verilog HDL
I2C
- iic协议 用verilog hdl语言，可以在xilinx ise软件 编译 综合-iic agreement verilog hdl language can be compiled in xilinx ise software integrated
URAT-code
- 使用Verilog HDL语言编写的URAT接口代码，实现串行数据传输功能-UART of Verilog HDL code to realize serial communication functio by Simon of Shenzhen University.
multiplier.v
- 依旧是自己写的一个8*8的乘法器的verilog代码，所以请大家下载，-Verilog still write their own code of an 8* 8 multiplier, so please download, thank you