资源列表
33162769crcm
- 基于FPGA的差错控制编码，CRC循环校验码的VHDL程序代码，含仿真文件-FPGA-based error control coding, CRC cyclic check code VHDL code, including simulation file
convolution
- This the code for the convolutional and the test bench for this in the verilog code.-This is the code for the convolutional and the test bench for this in the verilog code.
用 vhdl 设计含异步清零和同步时钟使能
- 用 vhdl 设计含异步清零和同步时钟使能的十进制加法计数器。再用 vhdl 设计含异步清零和同步时钟使能的十进制加减可控计数器。 -With vhdl design with asynchronous clear and synchronous clock enable decimal up counter. Vhdl design and then synchronize with asynchronous clear and clock enable control counter
A/D转换芯片TLC2543的verilog编程
- A/D转换芯片TLC2543的verilog编程，根据TLC5243的datasheet编写，程序简单，结构清晰，可以借鉴应用-A/D converter chip TLC2543 the verilog programming
TLC2543
- 使用Verilog实现的AD采样，很有用的！-Implemented using Verilog AD sampling, very useful!
fsk
- FSK 完整 支持两板间 通信 位同步 帧同步-FSK full support for communication between the two plates synchronization frame synchronization
TFTLCD
- 基于FPGA的彩屏LCD控制器，800*480，显示彩条，TFT LCD型号AT070TN83-The TFT Lcd controller based on FPGA.The Matrix is 800*480,it can display color bands.
ad5399
- AD5399是一款串行输入、双通道、12位数模转换器，可采用二进制补码数字编码。。 用Verilog实现其配置与功能-AD5399 is a serial input, dual-channel, 12-bit DAC, digital code can be twos complement. . Configuration and use Verilog functions to achieve its
8-bit_Alu
- This is a simple 8bit ALU that is coded in VHDL
Phase_Meter
- 无正负的带显示的周期信号相位差测量实现的程序代码-Unsigned band show the periodic signal code phase measurement achieve
verilog_pingpang
- verilog 语言的写的乒乓操作，通过两个寄存器实现。-verilog language, written in ping-pang operation, achieved through two registers.
ctc16
- 一个定时器/计数器，里面实现了两个定时计数器，每个都可以写入方式控制器，以实现定时或者计时功能！-A timer/counter, which implements two timer counters, each of which can be written mode controller to achieve the function of time or the time!