资源列表
uart_tx
- uart通信中的发送模块，在串口通信中，用于对外设进行通信，发送相应的指令，调节其时序逻辑。-uart communication sending module, in the serial communication, the communication of the peripheral and send the corresponding instruction, and to adjust its timing logic.
DCO_ST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
saomiao
- 基于vhdl语言的数码管动态扫描显示程序代码，同时加有数码管闪烁，超欠量程的led灯显示报警附加动能-Vhdl language-based digital control of dynamic scanning display program code, while adding a digital tube flashes, over and under range of led lights display alarm additional kinetic energy
Square-Root
- Square Root code in VHDL
I2S
- 本代码提供一种音频I2S读取数据的verilog代码，并且向fifo写入-This code provides an I2S audio data is read verilog code, and write to the fifo
hardware-rake_mrc1
- 采用硬件描述语言verilog进行RAKE MRC变换的实现的代码-Using hardware descr iption languages Verilog implementation ofRAKE MRC converter code
moore_in_and_mealy_out_state_machine
- 此程序为带摩尔输入、米勒输出状态的状态机控制部分-This procedure with Moore for input, Miller output state control of some of the state machine
vga_dis
- VGA的显示试验，这是在EPM240开发板上验证过的代码。-VGA display test, this is in the EPM240 development board validated code.
sine_package
- Sine wave generation Package
JIFENLBOQI
- 通过verilog hdl语言完成对积分梳妆滤波器的设计-By verilog hdl language used to complete the design of the integrator comb filter
ME
- the motion vector of the individual frame is estimated by using the cross search estimation algorithm
adgal
- 本代码可做为可编程逻辑器件ATF16V8B参考的例子，实现了各种 与或非逻辑