资源列表
pc104_fpga
- pc104接口的verilog代码，仅供参考-pc104 verilog interface code for reference purposes only
fifo_tb
- verilog implementation of 16X4 fifo with testbench
mamawithdisp
- this asm program is for 8051 used to control Dc motor in x and y axis direction with lcd-this asm program is for 8051 used to control Dc motor in x and y axis direction with lcd
DIVIDE_1_2_5_8_HZ
- pulse from 100MHz divided into several categories such as 1,2,5,8 Hz pulse
7duanshumaguan
- 7段数码管，显示计数器计数的个数，源代码简单，清晰-7-segment display counter counts the number of source code is simple, clear
AD652
- Clock generator for AD652-AEC. Generates switchbale 2,174MHz Clock
FPGA_PWM
- 用Verilog语言编写的FPGA控制PWM的程序.利用码盘脉冲进行调速,进行过简单试验,可用.没有经过长期验证.做简单修改即可应用!-Using Verilog languages FPGA control PWM procedures. Using pulse code disk for governor, conducted a simple test that can be used. Not after a long-term verification. To do a simple
chuanbingzhuanhuan
- 这个并串转换代码是依靠同步状态机来实现其控制的。其实并串转换在实际的电路中使用还是比较多的，尤其在通信线路方面的复用和分解方面，原理上就是一个串并转换和并串转换的过程。举个简单的例子，计算机串口发送数据的过程，如果满足发送条件了，其实就是一个并串转换的过程了。好了，废话不说，看代码就是。 -And the string conversion of the code is relying on the synchronization state machine to achieve its c
afficheur
- Driver d afficheur de 4 chiffres de sept segments
linearcode
- 基于FPGA的线性编码解码，verilog设计实现-FPGA-based linear encoding and decoding, verilog design and implementation
test_i2c_4
- Testbench file 4 for an i2c controlling an I2c slave device
ADC_TLC549
- 实现ADC转换的VHDL代码，利用计数器分频产生1MHz的频率，在此频率下，读取八位的AD数据并存储供处理使用，根据实际需要转换成模拟电平。-ADC conversion of the VHDL code, the use of counter divider to generate a 1MHz frequency, frequency, read eight of the AD data and stored for processing, according to the actual n