资源列表
vhdlexample
- vhdl的所有基本例子，对初学者很有帮助-vhdl all the basic examples, very helpful for beginners
music_vhdl
- 基于fpga和Quartus II的音乐播放器vhdl程序-Based on Quartus II fpga and vhdl music player program
Mult_Frequency
- Based on the verilog such as frequency meter accuracy, except for measuring frequency can also measure pulse width of empty measure than 32 counts of data through the simulation SPI serial output to SCM processing and display
trajectory_planning_2011_11_09
- 运用FPGA，创建NIOS2处理器，进行机器人逆运动学的轨迹规划，采用的是ALTERA 的飓风2处理器，处理速度非常快-The use of the FPGA, create NIOS2 processor, inverse kinematics, trajectory planning, the the ALTERA hurricane 2 processor, the processing speed is very fast
DE2_CCD_sobel
- verilog编写的适用于fpga的3x3模板sobel滤波-verilog fpga prepared for the 3x3 template sobel filter
ug230
- Xilinx Spartanman-3e starter kit user s mannual 含多种常见接口信息
MSP430-car-solution-with-Proteland-source-code
- MSP430小车解决方案含Protel和源代码.包括电动车跷跷板，简易智能电动车，悬挂运动控制系统，自动往返电动小汽车。-MSP430 car solution with Protel and source code. Seesaw including electric cars, Mini Mental electric vehicles, suspension motion control system, automatic and from the electric car.
SDRAM_96M
- 基于FPGA的SDRAM串口实验，verilog语言写的，附件里是做实验的工程，连上串口，下进去就有数据了，波特率9600，一个停止位，SDRAM时钟是96MHz，数据时FPGA自动产生的，正确输出结果是00到FF递增一，再循环。这个工程警告比较少，基本是故意为之的警告，时序也已经收敛。-FPGA-based SDRAM serial experiments, verilog language written annex is to do the experiment works, even o
Program
- 用ALTERA公司的FPGA写的网卡W5300程序-W5300 in fpga
PMSM-coder-angle
- 永磁同步电机编码器角度测量程序，verilog编程-The PMSM encoder angle program
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
dds_xu
- 直接数字频率合成器的VHDL完全源码，经测试可以正常使用，仿真正常-Direct Digital Frequency Synthesizer