资源列表
24_lcd_gui
- fpga源码，供初学者使用，GUI系统说明-fpga source code, for beginners, GUI System Descr iption
123
- 基于FPGA的简单计算器系统的设计，使用了vhdl与verilog语言，附有文档介绍-Simple calculator system based on FPGA design using vhdl verilog language, with document describes
Wiley[1].Advanced.FPGA.Design.Jun.2007
- a good book on fpga. useful for beginners
Wiley.Advanced.FPGA.Design.Jun.2007
- Advanced design for VHDL language
logic
- Verilog HDL逻辑与计算机设计基础实验全部试验报告，包括寄存器，定时器，全加器，同步时序电路，译码器等的实验。-Verilog HDL logic and computer design basic experiment all test reports, including registers, timers, full adder, synchronous sequential circuits, decoders and other experiments.
Detection0X47
- verilog DVB 扰码设计 0x47-verilog DVB- scrambling design
DSP_XINTF_FPGA
- DSP的XINTF功能和FPGA之间进行异步通信，调试通过，且运行稳定-Carried out between the DSP and the FPGA XINTF asynchronous communication functions, debugging, and stable operation
emif2mcbsp
- 在fpga上编写的emif和mcbsp接口程序，是一个项目的一部分，只是用于测试用，能正确传输数据-Emif and MCBSP interface program written on fpga, is a part of the project, just for test, to transmit data correctly
PerfectTiming
- 完美时序，含中英文两个版本！这应该是FPGA时序分析方面最经典最权威的书了，相信会对FPGA爱好者有很大用处！-Perfect timing, with two versions in English! This should be the most classic FPGA timing analysis the most authoritative book, that would be very useful FPGA lovers!
jtag_uart
- Configuration and usage of Altera s JTAG UART.
simProcessorEx
- 一个简单微处理器内核的VHDL程序，包含源代码（位于Source目录内）及ModelSim仿真代码（位于testBench目录内）。使用该内核进行一个功能验证程序（位于simProc_test目录内）-a simple processor core program and test code based on VHDL language
basketball_24time1
- 该文档主要是用verilog语言实现篮球24秒计时器，这是我做的数字电子技术课程的一次大作业。 里面为整个文件夹，解压之后可在Quartus13.0上直接运行。(This document mainly uses Verilog language to realize basketball 24 second timer, which is a big assignment of digital electronic technology course I do. It contains the