资源列表
crc16-
- 本文档描述了一种CRC校验的方法，开发语言为verilog。程序自己写的，包括测试代码。欢迎参考-This document describes a CRC checksum method development language verilog. Write their own procedures, including test code. Welcome reference
basic_1
- vhdl 语言实现序列检测器 -vhdl language sequence detector vhdl language sequence detector
bits
- verilog语言，移位寄存器实现的序列检测器-verilog language, to achieve the shift register sequence detector
modulation
- 基于FPGA的调制，实现了QPSK调制，所用芯片为Artera的CycloneIIEp2C5T114C8
VHDL
- 一个实现整数分频的VHDL代码，只要把n设置成你所需要的分频的数值就行-A realization of an integer divider of the VHDL code, as long as the n set you need the sub-frequency values on the line
CLZ_32bit
- 前导零的计算-Calculation of leading zeros
Universal-Register
- Octal D-Type Register with 3-State Outputs -- Simple model of an Octal D-type register with three-state outputs using two concurrent statements.
jiaoyan
- 使用VHDL硬件描述语言边写的奇偶校验程序和3-8译码电路程序
Basketball
- 此程序是关于篮球计数器的FPGA的代码，用的是ALTERA的板子
DDS
- AD9851的代码，采用串行的方式来实现。经过测试，可以使用-AD9851 code, serial way to achieve. After testing, you can use
delay
- PWM整流器的死区延迟的VHDL编程，可以参考一下-VHDL programming PWM Rectifier dead-band delays
8倍频vhdl
- 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software