资源列表
YCrCb2RGB
- 用verilo编写的RGB编码，而且加入了流水线
clock
- 用VHDL写的带有小时，分钟，秒的电子钟，已在FPGA开发板上调试运行过，显示very well!-Written in VHDL, with the hours, minutes, seconds, the electronic clock has been running in the FPGA development board debugger before, show very well!
Verilog_traffic_control
- verilog,交通灯控制器,包括左/右拐，红、黄、绿灯。-verilog, traffic light controllers, including the left/right, red, yellow, green.
async_transmitter
- RS232的FPGA code，利用Verilog實現傳輸的部分。
lock
- 数字密码锁，打开关闭，修改密码，密码锁存，重置-Digital code lock, turn off, change password, password latch reset
traffic-light-control-verilog-code
- 交通灯控制器verilog代码，实现交通灯的控制-traffic light control verilog code
FIX_ONE_ROW_ROM
- 此為文字型LCD顯示液晶透過矩陣與狀態機顯示內容-This is a text-based LCD display through matrix liquid crystal display with a state machine
register
- 简单8位移位寄存器的设计 设计较简单，仅供参考 免费的哦-Simple 8-bit shift register design is relatively simple design, for reference only free Oh
CPUtest
- AU3源码，CPU和内存检测工具，可用于系统部署-AU3 source, CPU and memory testing tool for system deployment
FIR_Direkt_ak
- VHDL代码的直接型FIR滤波器22阶。Fa=48 kHz, Fc=10kHz 可以在ModelSim下仿真， FPGA实现。 -VHDL code of the direct-type 22-order FIR filter. Fa = 48 kHz, Fc = 10kHz can be under the ModelSim simulation, FPGA realization.
fir_lpf
- 在FPFA上实现低通滤波,使用VERILOG编写-In FPFA to achieve low-pass filter, using VERILOG write
RCServo.v
- Generate RC SERVO PWM Verilog