资源列表
frequency---base-on-verilog
- 基于verilog的数字频率计设计(源码)-frequency design base on verilog
paobiao
- 本源码是用verilog编写的FPGA程序，其中包括了数字跑表模块和RS触发器模块。-The source code is written in verilog FPGA programs, including digital stopwatch module and the RS flip-flop modules.
Radix_4
- Verilog for radix algo
matlab-fft
- FFT的MATLAB的实现方式，自己试过，大家可以参考一下。-FFT MATLAB way to achieve their tried, we could take a look.
main
- altera de2 sd 卡源程序。调试成功的
lock
- 电子密码锁，实现并行输入，错误报警和密码设置功能，以及兼作门铃使用-Electronic code locks, the realization of parallel importation, error alarm function and password settings, as well as the use of doubles as a doorbell
ledcontrol
- FPGA驱动LED静态显示 --文件名：ledcontrol.vhd --功能：译码输出模块，LED为共阳接法 -FPGA-driven LED static display- File Name: ledcontrol.vhd- Function: decode the output module, LED is connected in a total of Yang
4step2iirfilter
- 用VerilogHDL实现一个阶数为4，两个支路的并行IIR滤波器，可以用同样的方法实现更多支路的滤波器。-With VerilogHDL order to achieve a 4, the two branches of the parallel IIR filter, the method can achieve more with the same branch of the filter.
pcm_slv_top
- 实现了verilog语言的pcm编码功能-verilog pcm module
Modulator70
- 个人参与的某国家工程并行排序MATLAB程序，用于FPGA的RTLAB仿真，使用Simulink工具生成HDL代码。测试可用。-Individuals involved in sort of a national engineering parallel MATLAB programs for the FPGA RTLAB simulation, using the Simulink tool to generate HDL code. Test available.
DIV_5
- 该源码包包含一个奇分频分频器的Verilog代码及其测试代码。奇分频在许多分频电路中都会用到。-The source code package contains a surprising frequency divider in Verilog code and test code. Odd number of points in the frequency divider circuit will be used in.
SEG
- 采用DE2 实现数码管递增 VERILOG-Using DE2 achieve the digital pipe incremental VERILOG