资源列表
synthesis
- Verilog code and some basic examples.
look-up-table-for-sine-wave-generation
- hi this an verilog codes-hi this is an verilog codes
verilog_k4s643232h_0401
- Samsung SDRAM Simulation Verilog
8LFSR
- 8阶LFSR,有文档介绍，算是比较好的一个了-8-order LFSR, a document describes the
pci
- fpga专用的pci接口软核，减少在开发过程中的周期！-dedicated fpga pci interface soft-core, reducing the cycle in the development process!
HowtousePerlinyourVerilogHDLDesignFlow
- use Perl in your Verilog HDL Design Flow,利用Perl语言方便管理Verilog HDL 代码。-How to use Perl in your Verilog HDL Design Flow
LCD1602
- ＬＣＤ１６０２在８０５１上的驱动，可在屏幕上显示任意字符-LCD1602 driver in 8051 can be any character on the screen
FPGA-jisuanqi
- 基于Verilog 语言的简易计算器的程序参考-design of jisuanqi
source
- 2. /qdr2/source/qdr2_io.v > Top level file includes declarations of HSTL1 and LVTTL I/O standards /qdr2/source/qdr2.v > Main module of the QDR memory controller /qdr2/source/pipeline.v > Pipeline module for increasing performance
4
- 设计一个轨道交通自动售票电路，只接受1，2，5元人民币，每张票价定额5元，并支持找零。要求： （1）用状态机方法设计；(Design an automatic rail transit ticketing circuit, accepting only 1, 2, 5 yuan, 5 yuan per ticket, and support change. Requirements: (1) design with state machine method;)
counter_verilog
- DE2_70_D5M_LTM_sobel_dilation
x264
- hwaccel = get_hwaccel