资源列表
Lab4
- 此為VHDL之同步清除電路與非同步清除電路之模擬與電路設計-This is a synchronous clear circuit VHDL synchronize with non-clear analog circuits and circuit design of
show
- DE2平台键控传输，完成PC机键盘控制，PS/2传输DE2目标板实现
edgedetece
- 边缘实现算法
tongxun
- CAN总线通信实例，SCI串口通信实例，快速以太网通信技术的应用实例，虚拟I2C总线软件包应用实例-CAN bus communication instance, SCI serial communication instance, an application example of the Fast Ethernet communication technology, virtual I2C total Instance of the line package applications
8w64fb
- 8位64个采样点的方波发生信号器。基于PFGA的采用PLL模块实现功能-8 of 64 samples of signal square wave device. The use of PLL-based PFGA module function
REG_show
- 利用程序实现红外线解码显示数据码和反码，并调用数码管显示，实现动态变化，动态显示，已调试。-The use of infrared decoding program code and inverted display data and call digital display, dynamic changes, the dynamic display, debugging.
lab2-original
- simple priority controller and decoder
VHDL3
- 这是一个自动售货机的vhdl源码，曾经是eda比赛的题目，供大家参考。-This is a vending machine in VHDL source code, the game had been sown topic, for your reference.
EDA
- EDA实验源代码、主要为加减计数器、译码器、编码器等-EDA test source code, mainly for the addition and subtraction counter, decoder, encoder, etc.
03_beep.rar
- 通过verilog语言，驱动无源蜂鸣器，实现建议电子琴的功能,Through verilog language, passive buzzer driver, the proposed implementation of the Electronic organ function
dds2_ok
- 利用LPM_ROM和HDL设计的一个DDS信号发生器，分辨率优于1HZ，ROM表长度8位，8位频率控制字。-HDL design using LPM_ROM and a DDS signal generator, the resolution is better than 1HZ, ROM table length 8 bits, 8-bit frequency control word.
07~chapter-04-atpg
- Slides from "VLSI test" book.