资源列表
cdma_sim
- cdma直接扩频系统，扩频码长度可配置，码速率可配置，仿真已经通过-CDMA
fpgafft
- 用fpga实现dsp 的fft算法 其中有几个文档文件和用vhdl写的1024点的fft代码
counter
- FPGA编程，用Verilog语言实现4位累加器功能-The FPGA programming, realize four accumulator with Verilog language features
FPGAFFT
- 1024个蝶形算法，将时域的性质转换到频谱-1024 butterfly algorithm
1616
- 16x16点阵,串行输入，显示“欢”字。-16 x 16 dot matrix
cic_compiler_ds613
- cic_compiler_ds613 xilinx technology documents
can-sja1000
- CAN总线开发代码，FPGA与sja1000通信，可实现CAN的接收和发送。-The FPGA and the sja1000 CAN bus development code, communication, which CAN realize the CAN send and receive.
IIR
- 气象雷达回波信号中杂波抑制的IIR算法（FPGA是实现的）-Weather radar echo signal of the IIR clutter suppression algorithm
iic
- i2c接口的功能实现代码，用VERILOG编写，并附有testbench.-i2c interface function implementation code, written in VERILOG, along with testbench
verilogdesign2
- 硬件描述语言设计相关，包括一些国外大学的教案和设计资料-verilog
LwIP_hw_platform_0_wrapper_0
- Vivado hardware platform files for sdk to implement LwIP
multiplier
- 使用硬核乘加器完成两路输入数据相乘，每8个乘积结果累加后输出-The use of hard core multiplier accumularor complete two-way input data is multiplied by each of the 8 product, the cumulative output results