资源列表
SPWM-generator
- 这是几篇关于产生SPWM波的方法的论文，希望对大家有所帮助！-there are some papers about the method of generating the SPWM waves .
PS2keyboard
- PS2键盘口扫描电路的实现 VHDL语言实现-PS2 keyboard port scanning circuit realization of VHDL language
lab4
- s the design and simulation of a simple traffic light controller: The controller consists of a clock divider block, two sequential circuits: a timing counter and a signal generator (state generator), and a decoder. The counter is used to define a
songer
- vhdl实现乐曲演奏,乐曲可以自行替换,led显示音调.-vhdl achieve music performances, music can replace on their own, led display tone.
fulladder
- 由四位全加器通过元件例化语句设计成十六位的全加器-By four full adder component instantiated by statements designed 16 of the full adder
Intel-Core-i3-i5-i7
- Intel Core i3，i5，i7.rar-Intel Core i3, i5, i7.rar
A402-OutputTFT-LCDDriverICWithPower
- 文档主要是关于TFT-LCD的相关资料，是有关TFT-lcd芯片的结构与设计理念，对于在这方面学习的朋友有比较大帮助-402 output thinfilm transistorliqu idcrystal display(TFT-LCDdriver integrated circui(ICwith power controlbasedon the number of color stobe displaye disdescribed. Toachievethistypeofpowercon
travel
- 自己做的vhdl课程设计，交通灯：实现主干道倒计时，分别为30,20,5秒，分情况：当主干道有车时，红黄绿交替，当只一个道路上有车时，那个道的交通灯变绿色，利用max+plus2做成，使用flex8000,epf8282alc84_4只用加一个38译码器模块即可，使用别的板子也可以运行-VHDL to do their own curriculum design, traffic lights: the realization of the trunk road countdown, 30,20
UART
- 使用标准VHDL编写的RS232协议，可在CPLD或者FPGA上直接实现串口通信功能。-use VHDL to implement RS232 protocol, which can be used in CPLD or FPGA
master_i2c
- 主I2C程序，完成LED读写,寄存器读写-master_i2c verilog
verilog
- 用verilog语言进行状态机的时序与功能仿真-Verilog state machine language with timing and functional simulation
Timer
- 假定系统时钟为50MHz，试设计一个电子秒表电路，使其按0.01s 的步长进行计时。该电子秒表具有异步清零和启动/停止计数功能，最大能计到59.99s，并用数码管显示计数值。用发光二极管显示向分钟的进位信号。-Assume that the system clock to 50MHz, the design of an electronic stopwatch test circuit, so the step by 0.01s to time. The electronic stopwatch