资源列表
Study_on_Key_Technologies_of_n4-DQPSK_Modulation_a
- 本文首先研究可4一DQPsK调制解调系统中调制部分的基本原理和各个模块的设计方案，重点研究成形滤波器和直接数字频率合成器 (DireetoigitalFrequeneySynihesis，简称DDS)，并针对各个关键模块算法进行matlab设计仿真，展示仿真结果。其次，研究调制解调系统解调部分的基本原理和各个模块的设计方案，重点研究差分解调，数字下变频和位同步算法，也针对其各个关键模块进行算法的Matlab设计仿真。然后用Matlab对整个系统进行理论仿真，得出结论。在此基础 上，采用超高速
my_ram_change
- 该文档实现了向BRAM中写入数据。1024个为一组，前1000个存1，后24个存0.共存入100组。-This document implements write data to the BRAM. 1024 as a group, the first 1000 deposit 1, deposit after 24 0 100 group were deposited.
IPcore
- FPGA 的各种 ip core 供大家参考-FPGA various ip core for your reference
AD6645_UART_DEMO_change
- AD6645 FPGA驱动程序，实现AD采样和uart传输-driver program for AD6645 on FPGA,and translated by UART
fpga_dsp_simple
- dsp和fpag通信的测试程序，包含整个工程和signaltap测试信号。-the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.
spi
- SPI Verilog code with programmable clock
led_test
- LED流水灯，4个流水灯，每隔一秒亮一次，4秒为一周期(LED water light, 4 water lights, every second, once, 4 seconds for a cycle)
PWM_extend
- 本代码采用RTL级的硬件描述语言设计了一个多通道的PWM波形捕获、输出模块。主要用在无人机或是其它需要控制多个伺候电机的场合。开发环境为Xilinx公司的ISE12.0。-This code uses RTL-level hardware descr iption language designed a multi-channel PWM waveform capture, output module. Mainly used in the need to control multiple un
clock-switch
- 自己编写的异步转同步的时钟切换，系统可以在两个时钟源之间切换运行。并附带仿真模型-I have written to synchronize asynchronous transfer clock switch, the system can be switched to run between two clock sources.
Foundry-Flash-Verilog-code
- 几大代工厂的flash verilog源代码-flash verilog code
AN136
- AMBA Application Note: AN136 - Using Core Tiles stand-alone. -AMBA Application Note: AN136- Using Core Tiles stand-alone. This example design shows how to use Core Tiles as individual units powered through an IM-LT1. A Logic Tile is also requi