资源列表
five
- 并入串出寄存器完成双向含异步清0和同步时钟使能的4位加法器的VHDL描述，并对其进行波形仿真，确定结果正确。- Incorporated into the string to the register to complete the two-way with asynchronous clear and synchronous clock so that the VHDL descr iption of the four adder energy and waveform simulatio
The-four-locks-Verilog-based-design
- 基于Verilog的四位密码锁设计，采用有限状态机进行编写-The four locks Verilog-based design, finite state machine for the preparation
USB_GPIF-II
- fpga模拟两路视频，简单拼接后，经过GPIF II接口传出给cy2014，测试usb的吞吐量-fpga generate two lane video, and transmit them through GPIF II interface. test cy2014
watch_dog_rtl_source
- watch dog written in vhdl and has been imp.
watch_dog_rtl_source
- Watchdog timer verilog RTL code
FPGA-verilog
- 用Verilog语言编写的一些简单的FPGA入门实验，用ALTERA DE2开发板和Quartus_II软件开发环境。包括：流水灯实验、数码管显示实验-With Verilog language preparation some simple introduction experiment, with FPGA ALTERA DE2 development board and Quartus_II software development environment. Include water l
200632814181169853
- 曼彻斯特编解码~VHDL?
ledtest
- 基于rvds的简单测试程序，运行的目标版是ok6410,led测试程序。-A simple test based on rvds program run target version is ok6410, led test program.
Verilog_Spike_Filter
- 实现Spike—滤波器的功能，可以经过quartus软件综合，然后映射到FPFGA上面-Achieve Spike-filter function, the software can be integrated through quartus then mapped to FPFGA top
fir_asm
- FIR滤波器设计 可以对输入信号进行FIR滤波 看到结果-FIR filter design FIR filter on the input signal to see results
Lab5.5_Led_FPGA
- 使用verilog在fpga开发板实现流水灯，包括整个工程文件-This code is used for early learners to study verilog。
Traffic-light-design
- (1) 能显示十字路口东西、南北两个方向的红、黄、绿的指示状态； • 用两组红、黄、绿三色灯作为两个方向的红、黄、绿灯，能实现正常的倒计时功能； • 用两组数码管作为东西和南北方向的到计时显示，显示时间为红灯55秒、绿灯50秒、黄灯5秒； *(2) 按S1键后，能实现特殊状态功能: • 显示到计时的两组数码管闪烁； • 计数器停止计数并保持在原来的状态； • 东西、南北、路口均显示红灯状态； • 特殊状态解