资源列表
uart_Verilog
- uart接口verilog源码，实现数据串并行的转换。内容包含十个代码文件。-uart Interface verilog source of data for serial-parallel conversion. Contains ten code files.
wave_genarator_vhdl
- vhdl波形发生程序.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -vhdl waveform occurred procedures. 4 achieve common sinusoidal waveform, 1.30, sawtooth, square-wave (A, B) the frequency and amplitude control
zhenxianyuxian
- zhe me duo shuo ming a da jia kan zhe xia zai ba-zhe me a duo shuo ming da jia kan zhe i gonna ba
TONGBUYIBU
- 同步复位和异步复位的区别 介绍非常详细 值得收藏-Synchronous reset and asynchronous reset of the difference
RS232_control
- verilog RS232信号解码模块。为在FPGA中的verilog代码。-verilog RS232 control module。
adder_ahead8bit
- 本文件提供了用verilog HDL语言实现的8位超前进位加法器,充分说明了超前进位加法器和普通加法器之间的区别.-using verilog HDL achieve the eight-ahead adder, fully demonstrates the CLA for ordinary Adder and the distinction between.
adder8-carryripple-adder
- 8位加法器，最基础的加法器。硬件语言 Verilog源代码。-8-bit carry-ripple adder, The basic adder and the common one. Achieved by Verilog source code.
source
- FPGA驱动八位数码管，做为16进制计数器。-16 counter,using verilog HDL
Behaviour-IP-Model-Flasys
- Behaviorial IP model flasys
7duanyimaguan-Verilog-HDL
- 7段译码管的Verilog HDL程序，希望对大家有用-7 segment decoder tube Verilog HDL procedures
Uart
- Uart总线，VHDL语言，硬件描述语言源码-Uart bus, VHDL language, VHDL source code
wave
- vhdl代码！ 波形发生程序！初学者可以参考参考-VHDL code! Programmed waveform! Beginners can refer to reference