资源列表
hspice
- this doc for hspice code beginners-this doc for hspice code beginners
1.-[Ebook]-Digital-Design-Principles-and-Wakerly-
- a good book about digital
FPGA_UWB
- 基于FPGA的UWB的发射系统.caj -UWB FPGA-based launch systems. Caj UWB FPGA-based launch systems. Caj
DE2_Default
- Altera DE2 demonstration design, lot of interesting verilog code for synthesis
Chapter_9
- E9_1_DPSKSignalProduc,FPGA实现的滤波器书的配套程序-E9_1_DPSKSignalProduc, FPGA realize filter book supporting program
DDS-SU
- 本程序采用了FPGA来控制DDS，采用并行方式，时序配置正确，成功地控制了DDS。可以作为初学者的参考。-DDS can produce all types and frequency and various amplitude modulated signals, but also to ensure the continuous phase, so it is widely used, but there may be doubt as to control for beginners DD
hsk4571_clock
- 数字时钟 VHDL实现，可调节时分秒，在QUATTUS||9.0下编写，可在9.0及以上版本运行并下载，芯片为Altera的Cyclone3 EP3C8T1-Digital clock VHDL realization, minutes and seconds can be adjusted in QUATTUS | | 9.0 under preparation, can be run in the 9.0 and above versions and download, chips for
lab1-lab3
- XILINX EDK中三个简单的实例！有PDF详细说明-XILINX EDK in three simple examples! A PDF details
clk_div
- ＦＰＧＡ Ｖｒｉｌｏｇ ＨＤＬ 分频器 输入３３ＭＨＺ ，输出１ＫＨＺ－５０ＨＺ-FPGA Vrilog HDL divider input 33MHZ, output 1KHZ-50HZ
CycloneIII_EP3C40F780C8_25_USB2_Test
- SOPC,CycloneIII系列芯片EP3C40F780C8，NIOS II IDE,USB 2.0 c测试实验代码 -SOPC,CycloneIII，EP3C40F780C8，NIOS II IDE, USB2.0 code
Circuit-Design-with-VHDL
- it is usful book for VHDL
MIT_Press_Circuit_Design_With_VHDL
- Programming for VHDL