资源列表
EXP2
- Quartus II开发SOPC拨挡开关、按键及LED-Allocated block switches, buttons, and LED
PciCore
- xilinx官方PCIcore 有详细说明文档，支持Spartan，Vertex
verilog_logic
- 基本逻辑运算，Verilog实现，带有实现教程。-Basic logic operations, Verilog implementation, with the realization of tutorials.
dds_work
- verilog语言编写，在Quartus II里仿真DDS的产生，包括所有仿真生成的相关文件--verilog language in the Quartus II DDS in the generation of simulation, including all documents generated by the simulation,
s3esk_microblaze_lcd
- 基于spartan3e的LCD显示程序,可直接将其bit文件烧写到spartan3e里面即可使用
IC035os142_min_minuse
- 数字电路设计，基本单元逻辑综合库，Worsst case 负温度，极端条件库，可用dc_shell 环境下调用进行RTL综合。-Digital circuit design, the basic unit logic synthesis libraries, Worsst case negative temperature, extreme conditions, libraries, available dc_shell environment called for RTL synthesis
PipelineCPU
- 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt
TEST_V5_MAC
- XILINX ML507开发板的网口信,microblaze, TEST_V5_MAC-XILINX ML507 development board network port communications,microblaze,TEST_V5_MAC
FPGA-DDS
- 基于FPGA的DDS实现QuartusII工程和论文-Based on the FPGA DDS QuartusII project and paper
DE2_ControlPanel_V2.0.1
- de2 Cyclone® II 2C35 FPGA 最新版 控制面板-de2 Cyclone® II 2C35 FPGA control pad
jianpan
- 用FPGA单片机软核实现键盘扫描，键盘为4X4矩阵键盘，输入相应键值，用数码管显示-keyboard
TimeClock
- 能够在max3上显示24小时，并且具有定时功能，能够设定闹钟，具有正点报时-Max3 can display 24 hours, and has a timer function, be able to set the alarm, with punctual timekeeping