资源列表
Synopsys_90nm_lib_course-OpenSPARC
- 开源可扩充处理器架构.源代码Synopsys_90nm_lib_course-OpenSPARC_labs_final_041509-Synopsys 90nm lib course-OpenSPARC labs final 041509
Verilog
- Verilog教程，不知道没有人传过
ARM_register
- ARM寄存器的设计，南京大学计算机系计算机组成原理实验内容-ARM register designs, Nanjing University Department of Computer Science, Principles of Computer Organization experiment content
d
- 实现了基于CycloneII的信号相位、频率测量-Achieve a signal based CycloneII, phase, frequency measurement
VHDLProgram36MHz
- 可以受上位机控制的通过fpga的视频信号发生器程序，可控制屏幕上产生各种运动图像
t48u_latest.tar
- The T48 μController core is an implementation of the MCS-48 microcontroller family ar-chitecture. While being a controller core for SoC, it also aims for code-compatability and cycle-accuracy so that it can be used as a drop-in replacement for any
FPGADM9000AVerilog
- FPGA控制DM9000A进行以太网数据收发的Verilog实现-FPGA control DM9000A Ethernet data transceiver Verilog realize
PCF8591VHDL-CODE
- PCF8591vhdl语言实现，能实现对8591的控制及数据采集。-PCF8591vhdl language, to achieve the 8591 control and data acquisition.
verilog_code
- verilog的大量实例，可以供初学者使用-a large number of instances of verilog
FPGA(QII)
- 数字信号发生器，FPGA做的仿真程序，包含三角波、锯齿波、正弦波、方波等共六种波形。-FPGA AND alter SIN SAN JIAO BO JUCHIBO FANG BO
div_3
- 用Verilog实现时钟三分频，该代码包含完整的工程文件，可直接运行。-The realization of clock frequency of three Verilog, the code contains the complete engineering documents, can be directly run.
YINYUEBOFANGQI
- 本程序是一个基于VHDL的音乐播放器学习资料，适合初学者学习-YINYUE BO FANG QI