资源列表
5-example_IR_1
- 基于altera EP4C FPGA的红外解析,协议格式为NEC protocol-FPGA, EP4C, NEC protocol
DM9000AaPC
- 用verilog语言完成的基于FPGA的DM9000A驱动，完成与PC的10M/100M通信-Using Verilog language to complete the FPGA DM9000A driver based on 10M/100M communication, complete with the PC
quartus_works_second
- 基于verilog语言的，FPGA程序，实现频率计与数码管显示功能，转换频率48M，精度1Hz，量程1Hz~9999Hz，有欠频率和超频率提示，精度与量程可随外部设备改变而改变，在EP1C3T100C8上亲测通过-Based verilog language, FPGA procedures to achieve frequency meter with digital display, switching frequency 48M, precision 1Hz, range 1Hz ~ 99
add-an-IP-to-EDK-hardware-design
- EXCD-1 可编程片上系统 实验例程中的EDK部分 功能：添加一个IP 到硬件设计-EXCD-1 programmable system on chip experimental part of the routine to add an IP to EDK hardware design
XilinxAdvancedFPGACourse
- xilinx官方推出的基于xilinx FPGA的高级设计的教程，适合较高级别的FPGA开发人员参考和学习。-xilinx the official launch of the advanced design based on xilinx FPGA tutorial, suitable for a higher level of FPGA developers to reference and learning.
phone
- 用DE0开发板实现电话计费器，基本功能：可设置通话模式，能初始化话费余额，拨动开关可进入通话模式，并根据通话时间和相应通话模式扣除相应的费用。通话过程中能够通过开关切换显示通话时间和话费余额，并可暂停通话。压缩包里有详细的WORD文档的说明，包括波形仿真和DE0的引脚功能介绍。-Implemented by DE0 board telephone billing, basic function: to set the call mode, you can initiate credit bala
VGA
- xilixnx FPGA 驱动640*480显示器显示红绿蓝色条，并在左上角显示一幅200*200像素图片(Xilixnx FPGA drives 640*480 display to display red, green and blue stripe.)
fre_pha_measure
- 实现了基于cycloneII的信号相位、频率测量，经测试可用-CycloneII based on the realization of the signal phase, frequency measurement, the test can be used
Digital_VLSI_Design_with_Verilog_1
- very useful design for fifo freshman
reed123
- Reedsolomon code verilog document--Reedsolomon code verilog document-VVV
FPGA-training-materials
- 交大FPGA培训资料,详细介绍FPGA的应用开发，是交大的内部培训资料-National Chiao Tung University FPGA training materials, details of the FPGA application development, is the National Chiao Tung University s internal training materials
veriloghdl
- 关于vhdl很好的一个课件，希望对大家有用-On a VHDL good courseware, in the hope that useful