资源列表
8051_IP
- 基于8051单片机IP软核的优化设计及应用研究-805IPsoftcorebasedonOptimaDesignandApplication
51SCMTutorial
- 《精彩51单片机教程》适合初学者，很难得-" Discover the 51 SCM Guide" for beginners, very rare
DualPortRAM
- 此程序是Verilog HDL语言读写RAM的程序希望大家有用-This is Verilog HDL Promang
20FIRFilterDecimal
- 20阶FIR数字滤波器，参数没有进行倍数扩大，参数经过CSD编码处理-20-order FIR digital filter, the parameter no multiple expansion, parameter encoding process after CSD
20FIRfilterwithCSD
- 20阶FIR滤波器，用CSD编码对参数进行了设计-20-order FIR filter with CSD coding of the design parameters
answermachine5
- 这次设计的抢答器主要四部分组成，由优先编码器，寄存器和译码器组成的抢答电路，十进制计数器组成的倒计时电路，555定时器组成的秒脉冲发生器，十六进制计数器组成的计数器。-The design of the Responder mainly of four parts, by the priority encoder, register, and the composition of the answer in the decoder circuit, consisting of decimal c
m7000
- m7000是FPGA的一种主要的芯片，该文比较适合初学者阅读-m7000
NIOSIIREV[1].0.2
- 一个很不错的学习FPGA NIOSII学习资料-A very good learning materials learning FPGA NIOSII
subtractor4
- Verilog half subtractor module and tests build with made with gates built with expression modules.
subtractor3
- Verilog 3bit full subtractor module and tests build with predefined nor gates.
subtractor2
- Verilog full subtractor module and tests build with a half subtractor made with predefined nand gates.
subtractor
- Verilog source code for full subtractor module build with predefined nor gates.