资源列表
CoreSPI
- 数字电子设计fpga设计的spi接口的ip_core，可以直接用于在fpga设计，支持actel的fpga芯片，支持主从模式，fifo大小可选。-Fpga design of digital electronic design spi interface ip_core, fpga design can be directly used to support actel the fpga chip, support master-slave mode, fifo size options.
modesim
- 讲述使用modelsim进行验证，使用verilogHDL语言进行建模。其中还包括一个讲述怎样用verilog语言编写测试台的详细文档，对fpga cpld设计的后期验证有很大的帮助。-About the use modelsim for authentication, use verilogHDL language modeling. It also includes a focus on how to use verilog test bench written a detailed doc
AVHDLPrimerBhasker
- VHDL developers can use this book to know more about it...
FIFO
- FIFO control in the FPGA-FIFO control in the FPGA
sdramc_vhdl
- Xilinx提供的SDRAM控制器参考设计（VHDL)-SDRAM controller reference design (VHDL) designed by Xilinx
Digital_VLSI_Design_with_Verilog_1
- very useful design for fifo freshman
Xilinx_FPGA_minsystem_XC3S400_USB2.0
- Xilinx_FPGA_最小系统原理图_XC3S400_+_USB2 实用-Xilinx_FPGA_minsystem _XC3S400_+_USB2
grlib
- gaisler lib. Format .vhd
8051_appnote_105
- 8051 timer tick interrupts
testps2
- 基于xilinx excd开发板的PS/2键盘计算器，能完成1位数据的加减乘除，功能可扩展-it s a ps/2 keyboard caculator
SEGcore
- 基于MICROBLAZE的数码管扫描IP核，在EXCD开发板上调试通过，可移植至其他开发板-An IP core based on microblaze,it is used for leds scanning
PWMcore
- 基于xilinx FPGA软核microblaze编写的PWM波产生IP核，在EXCD开发板上调试通过，内附UCF文件和说明-it s an IP core based on microblaze,it can produce pwm wave.