资源列表
DE2_LTM_Ephoto
- altera DE2+ TERASIC 触摸屏照片展示例程-altera DE4+ TERASIC photo touch-screen display routine
keyscanverilog
- 基于DE2-70开发板的四个按键KEY0-KEY3的按键检测程序，可控制跑马灯的方向和运行-Based on the DE2-70 development board of four key KEY0- KEY3 test procedures, can control the direction of the entertaining diversions and run
zucheng
- 部分指令系统和三态门用VHDL在模型机上的实现-Part of the command system and the tri-state gate analog implementation
DIPC1.zip
- 5/3小波变换的vhdl代码实现，可以供参考，,5/3 wavelet transform vhdl code, you can for information,
snake_VHDL
- 基于vhdl编写的贪吃蛇游戏，课程设计必备-Based on the VHDL language of the snake game, curriculum design essential
sin_gen
- 弦波產生+七段顯示器顯示目前該弦波點之數值-have grounded in paragraph 107 of the display shows the current Numerical grounded point
ans
- 数字式竞赛抢答器 实现功能 1.四路抢答功能，带抢答超时和答题超时功能； 2.计分显示功能，每组对应两个数码管，能显示0-99的分值，复位初值为10。 -Digital Competition Responder features a realization. Quad Responder function, with time out and answer time-out function Responder 2. Scoring display, each corres
lcd1621
- 在LCD上显示事先就输入好的字符,可以任意改变的-displayed on the LCD on the admission of prior good character, can be arbitrarily changed by the
AnalogandMixedSignalModelingusingVHDL
- The Design Entity is the basic building analog block of a VHDL descr iption.
RTC
- VHDL 非常好的日历时钟学习源码资料,-RTC learn VHDL very good source of information
frame-synchronous-search-circuit
- 用verilog语言编写的帧同步搜索电路，输入数据data为8 bit并行数据流，基本结构为数据帧，帧长为10字节，帧同步字为H“FF”。clk为输入同步时钟。-Verilog language for frame synchronous search circuit, the input data is data for the 8-bit parallel data stream, the basic structure of the data frame, the frame lengt
M_ACTION1
- 使用fpga实现任意长度，任意方程的伪随机系统码-Using FPGA to achieve arbitrary length, any equation of the pseudo random system code